$TITLE ('RTX-51 SYSTEM DATA')
$SYMBOLS
$NOXREF
$NOCOND
$NOMOD51
$NORB
$PAGELENGTH (80) PAGEWIDTH(110)
;************************************************************************
;*									*
;*    R T X - 5 1  :   SYSTEM DATA                                      *
;*							     		*
;*----------------------------------------------------------------------*
;*                                                                      *
;*    Filename     :   RTXDATA.A51                                      *
;*    Language     :   Keil A-51                                        *
;*    Dev. system  :   Keil uVision2                                    *
;*    Targetsystem :   Any system based upon 8051 up                    *
;*                                                                      *
;*    Purpose      :   Declaration of all RTX-51 variables              *
;*								     	*
;*----------------------------------------------------------------------*
;* Rev. |  Released   | Programmer    | Comments                        *
;*----------------------------------------------------------------------*
;*  0.1 |  16.1.90    | E. Glatz      | Changes for V3.18               *
;*  0.2 |   8.3.91    | Th. Fischler  | C-51 calling conventions        *
;*      |             |               | PL/M-parameter segment          *
;*      |             |               | eliminated                      *
;*      |  28.3.91    | Th. Fischler  | Task-Names eliminated           *
;*      |   5.4.91    |               | More changes for V4.0           *
;*      |  19.9.91    |               | Supervisor-mode flag added      *
;*      |  20.9.91    |               | Variables for memory-pools      *
;*      |             |               | added                           *
;*      |   9.10.91   | Th. Fischler  | internal_num_table added        *
;*      |             |               | rtx_int_count removed           *
;*      |  19.11.91   |               | rtx_disp_tmp5 added             *
;*      |  13.04.92   | Th. Fischler  | Bit ?RTX_BANKSW added           *
;*      |  27.10.92   | Th. Fischler  | Variable ?RTX_P2_MIR added      *
;* 5.0  |  10.10.94   | E. Glatz      | Sema. support, optional mbx and *
;*      |             |               | pages (-> RTXCONF), intervallist*
;*      |  12.10.94   |               | Comments about restrictions     *
;* 7.00 |  13.11.2001 | T. Mueller    | Release 7.00                    *
;************************************************************************
;*    Copyright 1991 .. 2001 METTLER  &  FUCHS  AG,  CH-8953 Dietikon   *
;************************************************************************

$INCLUDE (RTXCONST.INC)


;*----------------------------------------------------------------------*
;*	E X P O R T S
;*----------------------------------------------------------------------*

;       Relocatable bitaddressable byte segment
;
PUBLIC  ?RTX_BIT_RELBYTE_BEG
PUBLIC  ?RTX_RUNNING_TID, ?RTX_TMP0
PUBLIC  ?RTX_BIT_RELBYTE_END

;       Relocatable byteaddressable byte segment
;
PUBLIC  ?RTX_RELBYTE_BEG
PUBLIC  ?RTX_TMP1, ?RTX_TMP2, ?RTX_TMP3, ?RTX_TMP4, ?RTX_TMP5, ?RTX_TMP6
PUBLIC  ?RTX_DISP_TMP1, ?RTX_DISP_TMP2, ?RTX_DISP_TMP3
PUBLIC  ?RTX_DISP_TMP4, ?RTX_DISP_TMP5
PUBLIC  ?RTX_ACT_LIFO_EL, ?RTX_P2_MIR
PUBLIC  ?RTX_RDY_COUNT0, ?RTX_RDY_COUNT1, ?RTX_RDY_COUNT2, ?RTX_RDY_COUNT3
PUBLIC  ?RTX_RDY_FIRST0, ?RTX_RDY_FIRST1, ?RTX_RDY_FIRST2, ?RTX_RDY_FIRST3
PUBLIC  ?RTX_RDY_LAST0, ?RTX_RDY_LAST1, ?RTX_RDY_LAST2, ?RTX_RDY_LAST3
PUBLIC  ?RTX_SAVE_INT_A, ?RTX_SAVE_INT_B, ?RTX_SAVE_INT_DPL, ?RTX_SAVE_INT_DPH
PUBLIC  ?RTX_SAVE_INT_PSW, ?RTX_SAVE_INT_SP, ?RTX_SAVE_INT_TID, ?RTX_SAVE_INT_RSP
PUBLIC  ?RTX_SYSCLK_COUNT
$IF (DBG = 03H)
   PUBLIC  ?RTX_SYSCLK_COUNTHI
$ENDIF
PUBLIC  ?RTX_RELBYTE_END

;       Bit segment
;
PUBLIC  ?RTX_PROCESSOR_ALLOCATED, ?RTX_REQ_REDISPATCH, ?RTX_SYSCLK_ISR, ?RTX_FULL_CONTEXT
PUBLIC  ?RTX_REENTRANTFLAG, ?RTX_ENA_INT_REG1, ?RTX_ENA_INT_REG2
PUBLIC  ?RTX_ROUND_ROBIN_REQ, ?RTX_ROUND_ROBIN_OK
PUBLIC  ?RTX_SUPERVISOR_MODE, ?RTX_SAVE_INT_SV, ?RTX_BANKSW
PUBLIC  ?RTX_MBX_SUPPORT, ?RTX_SEM_SUPPORT
$IF (DBG = 01H)
   PUBLIC BUSY_FLAG, LOCK_FLAG, SYSOP_FLAG, CLOCK_FLAG
$ENDIF
$IF (DBG = 02H)
   PUBLIC BUSY_FLAG
$ENDIF

;       XDATA segment
;
PUBLIC  ?RTX_SYS_PAGE
PUBLIC  ?RTX_INT_TID_TABLE_BASE
PUBLIC  ?RTX_INT0_TID, ?RTX_INT1_TID, ?RTX_INT2_TID, ?RTX_INT3_TID
PUBLIC  ?RTX_INT4_TID, ?RTX_INT5_TID, ?RTX_INT6_TID, ?RTX_INT7_TID
PUBLIC  ?RTX_INT8_TID, ?RTX_INT9_TID, ?RTX_INT10_TID, ?RTX_INT11_TID
PUBLIC  ?RTX_INT12_TID, ?RTX_INT13_TID, ?RTX_INT14_TID, ?RTX_INT15_TID
PUBLIC  ?RTX_INT16_TID, ?RTX_INT17_TID, ?RTX_INT18_TID, ?RTX_INT19_TID
PUBLIC  ?RTX_INT20_TID, ?RTX_INT21_TID, ?RTX_INT22_TID, ?RTX_INT23_TID
PUBLIC  ?RTX_INT24_TID, ?RTX_INT25_TID, ?RTX_INT26_TID, ?RTX_INT27_TID
PUBLIC  ?RTX_INT28_TID, ?RTX_INT29_TID, ?RTX_INT30_TID, ?RTX_INT31_TID
PUBLIC  ?RTX_RDY_PRIO0, ?RTX_RDY_PRIO1, ?RTX_RDY_PRIO2, ?RTX_RDY_PRIO3
PUBLIC  ?RTX_RDY_PRIO0_END, ?RTX_RDY_PRIO1_END, ?RTX_RDY_PRIO2_END
PUBLIC  ?RTX_RDY_PRIO3_END, ?RTX_STATE_TABLE
PUBLIC  ?RTX_MBX_CONTROL_BASE
PUBLIC  ?RTX_SEM_TOKENS
PUBLIC  ?RTX_SYS_PAGE_END

PUBLIC  ?RTX_AUX_PAGE
PUBLIC  ?RTX_DEBUG_TID, ?RTX_TID_TABLE, ?RTX_KNTXT_PTR_TABLE
PUBLIC  ?RTX_DELAY_LIST_CLK, ?RTX_DELAY_LIST_TID, ?RTX_SYS_TICK
PUBLIC  ?RTX_INTERVAL_LIST
PUBLIC  ?RTX_ISR_LIFO, ?RTX_POOL_CONTR, ?RTX_INTERNAL_NUM_TABLE
PUBLIC  ?RTX_AUX_PAGE_END


;*----------------------------------------------------------------------*
;*	I N T.   R A M   D A T A   D E C L A R A T I O N S
;*----------------------------------------------------------------------*

;---------------Byte Data in bit-segment---------------------------------

?RTX?RTX_BIT_RELBYTE_SEG SEGMENT DATA BITADDRESSABLE
                         RSEG    ?RTX?RTX_BIT_RELBYTE_SEG

?RTX_BIT_RELBYTE_BEG: DS      0
;
;	The following bytes must be in bit-addressable DATA memory
;
?RTX_RUNNING_TID:     DS      1   ; Task_ID of currently running task
                                  ; (bit-addressable)
?RTX_TMP0:            DS      1   ; Temporary var. for RTX interbal use
                                  ; (bit-addressable)
                                  ; (during sections where ?RTX_TMP0 
                                  ;  contains data task interrupts must 
                                  ;  be disabled !)
?RTX_BIT_RELBYTE_END: DS      0



;---------------Byte Data in data-segment--------------------------------

?RTX?RTX_RELBYTE_SEG SEGMENT DATA
                     RSEG    ?RTX?RTX_RELBYTE_SEG

?RTX_RELBYTE_BEG: DS     0
;
;	These byte variables may be located anywhere in DATA memory
;
;
;       ?RTX_TMP1..6:   - used for temp. storage by different RTX functions
;                       - during program sections where they contain data
;                         to be preserved task interrupts MUST BE DISABLED
;                         (i.e. during parameter passing or regions where
;                          they are used to save any values)
;       
?RTX_TMP1:      DS      1       ; These temp. storage variables must be
                                ; accessed with task interrupts disabled,
?RTX_TMP2:      DS      1       ; because they are common for all tasks and
                                ; are used by several RTX modules. During
?RTX_TMP3:      DS      1       ; program sections where they contain data
                                ; task interrupts must be disabled !
?RTX_TMP4:      DS      1
?RTX_TMP5:      DS      1
?RTX_TMP6:      DS      1
       
?RTX_DISP_TMP1: DS      1       ; Temp. var. for RTXDISP (do NOT use elsewhere)
?RTX_DISP_TMP2: DS      1       ; Temp. var. for RTXDISP (do NOT use elsewhere)
?RTX_DISP_TMP3: DS      1       ; Temp. var. for RTXDISP (do NOT use elsewhere)
?RTX_DISP_TMP4: DS      1       ; Temp. var. for RTXDISP (do NOT use elsewhere)
?RTX_DISP_TMP5: DS      1       ; Temp. var. for RTXDISP (do NOT use elsewhere)

?RTX_ACT_LIFO_EL: DS    1       ; ISR-LIFO pointer

?RTX_P2_MIR:    DS      1       ; Mirror of the P2 register

;
;	Variables for list management of the ready-list
;	(1 FIFO Buffer for each priority)
;
?RTX_RDY_COUNT0:     DS      1       ; Element counter  (FIFO 0)
?RTX_RDY_FIRST0:     DS      1       ; Pointer to first element (FIFO 0)
?RTX_RDY_LAST0:      DS      1       ; Pointer to last element (FIFO 0)

?RTX_RDY_COUNT1:     DS      1       ; Element counter  (FIFO 1)
?RTX_RDY_FIRST1:     DS      1       ; Pointer to first element (FIFO 1)
?RTX_RDY_LAST1:      DS      1       ; Pointer to last element (FIFO 1)

?RTX_RDY_COUNT2:     DS      1       ; Element counter  (FIFO 1)
?RTX_RDY_FIRST2:     DS      1       ; Pointer to first element (FIFO 1)
?RTX_RDY_LAST2:      DS      1       ; Pointer to last element (FIFO 1)

?RTX_RDY_COUNT3:     DS      1       ; Element counter  (FIFO 1)
?RTX_RDY_FIRST3:     DS      1       ; Pointer to first element (FIFO 1)
?RTX_RDY_LAST3:      DS      1       ; Pointer to last element (FIFO 1)

?RTX_SAVE_INT_A:     DS      1       ; Save area for suspended task con-
?RTX_SAVE_INT_B:     DS      1       ; text
?RTX_SAVE_INT_DPH:   DS      1
?RTX_SAVE_INT_DPL:   DS      1
?RTX_SAVE_INT_SP:    DS      1
?RTX_SAVE_INT_PSW:   DS      1
?RTX_SAVE_INT_TID:   DS      1
?RTX_SAVE_INT_RSP:   DS      2       ; reentrant stack-pointer

?RTX_SYSCLK_COUNT:   DS      1       ; Counter for system clock, 
                                     ; range=[0..0FEH], 0FFH invalid !

$IF (DBG = 03H)
   ?RTX_SYSCLK_COUNTHI: DS      1    ; For time logging
$ENDIF

?RTX_RELBYTE_END: DS     0



;---------------BIT data------------------------------------------------

?RTX?RTX_BIT_SEG     SEGMENT BIT
                     RSEG    ?RTX?RTX_BIT_SEG
;
;	Flags for RTX system use
;
?RTX_PROCESSOR_ALLOCATED: DBIT 1     ; =0: deallocated, =1: allocated
?RTX_REQ_REDISPATCH:      DBIT 1     ; =1: request for redispatch set
                                     ; =0: request for redispatch reset  
?RTX_SYSCLK_ISR:          DBIT 1     ; =1: system clock ISR active, =0: inactive
?RTX_FULL_CONTEXT:        DBIT 1     ; Flag for context type (used by RESIGN)
?RTX_ROUND_ROBIN_REQ:     DBIT 1     ; Round robin flag for dispatcher
?RTX_ROUND_ROBIN_OK:      DBIT 1     ; Internal Flag for Dispatcher
?RTX_REENTRANTFLAG:       DBIT 1     ; =1: reentrant functions in system
                                     ; (initialised by RTXINIT)
?RTX_BANKSW:              DBIT 1     ; =1: RTX-51 with Code-Bank-Switching
                                     ; (initialised by RTXINIT)
?RTX_SUPERVISOR_MODE:     DBIT 1     ; Supervisor-mode flag
?RTX_SAVE_INT_SV:         DBIT 1     ; Save area for supervisor-mode flag
                                     ; for suspended task
?RTX_MBX_SUPPORT:         DBIT 1     ; Flag for mailbox support
                                     ; =1: mailbox FIFO's exist
                                     ; =0: mailbox FIFO's do not exist
                                     ; (initialised by RTXINIT)
?RTX_SEM_SUPPORT:         DBIT 1     ; Flag for semaphore support
                                     ; =1: semaphore FIFO's exist
                                     ; =0: semaphore FIFO's do not exist
                                     ; (initialised by RTXINIT)


; The following two bits enable the second and third interrupt enable register
; They will be initialised by the module RTXCONF (as part of the subroutine
; ?RTX_INIT_INT_REG_FLAGS; declared in RTXCONF and called by RTXINIT)
?RTX_ENA_INT_REG1:        DBIT 1   ; =0: no second interrupt enable Register
                                   ; =1; with second interrupt enable Register
?RTX_ENA_INT_REG2:        DBIT 1   ; =0: no third interrupt enable Register
                                   ; =1; with third interrupt enable Register


$IF (DBG = 01H)
   ;
   ;    Debug flags (declared on port pins, active for debug versions only)
   ;
   ;
   BUSY_FLAG     BIT     BUSY_FLAG_ADR   ; =0 : idle (no task running)
                                         ; =1 : currently executing a task
                                         ; This flag can be assigned to a
                                         ; port pin to which a LED is
                                         ; connected.
                                         ; This flag is set to 0 by the
                                         ; GET_RDY function when no ready
                                         ; task exists and set to 1
                                         ; by the interrupthandler.
   LOCK_FLAG     BIT     LOCK_FLAG_ADR   ; = 0 : interrupts globally enabled
                                         ; = 1 :     "         "     locked
   SYSOP_FLAG    BIT     SYSOP_FLAG_ADR  ; = 0 : user task running
                                         ; = 1 : system function running
   CLOCK_FLAG    BIT     CLOCK_FLAG_ADR  ; = 0 : system clock handler running
                                         ; = 1 : sys. clock handler not running
$ENDIF

$IF(DBG = 02H)
   BUSY_FLAG     BIT     BUSY_FLAG_ADR   ; =0 : idle (no task running)
                                         ; =1 : currently executing a task
$ENDIF



;*----------------------------------------------------------------------*
;*	E X T.   R A M   D A T A   D E C L A R A T I O N S
;*----------------------------------------------------------------------*

;---------------SYSTEM_PAGE------------------------------------------

?RTX?RTX_SYS_PAGE    SEGMENT XDATA INPAGE
                     RSEG    ?RTX?RTX_SYS_PAGE

?RTX_SYS_PAGE:       DS      0
;
;       Task State Table
;       ----------------
;       Array of state blocks, each of size 4 Byte. Index is task number.
;       Usage:  BYTE0           wait bits, signal flag, sem/mbx no for wait
;               BYTE1.7         wait bit
;               BYTE1.0..6      enable mask for IE.0..6 (IE.7=1 by default)
;               BYTE2           enable mask IEN1  
;               BYTE3           enable mask IEN2  
;
?RTX_STATE_TABLE:    DS      4*TASK_COUNT    ; For 16 non-driver and 3 driver tasks
;
;       Ready List FIFOs
;       ----------------
;
?RTX_RDY_PRIO0:      DS      16              ; Ready list FIFO for prio. = 0
?RTX_RDY_PRIO0_END:
?RTX_RDY_PRIO1:      DS      16              ; Ready list FIFO for prio. = 1
?RTX_RDY_PRIO1_END:
?RTX_RDY_PRIO2:      DS      16              ; Ready list FIFO for prio. = 2
?RTX_RDY_PRIO2_END:
?RTX_RDY_PRIO3:      DS      16              ; Ready list FIFO for prio. = 3
?RTX_RDY_PRIO3_END:

;
;	Mailbox and Semaphore Control Blocks
;       ------------------------------------
;
;       Restriction: - each block must have a size of 8 byte
;                      (assumed by many in-line code parts for index
;                       calculation)
;       
;       6 bytes of each block are dedicated to mailbox control,
;       2 bytes of each block are dedicated to semaphore control
;
;       Array of control blocks, each control block has the structure:
;
;       byte0:  mbox info-list counter
;       byte1:  mbox T-list counter
;       byte2:  mbox first el. ptr. of Info-list
;       byte3:  mbox last el.+1 ptr. of Info-list
;       byte4:  mbox first el. ptr. of T-list
;       byte5:  mbox last el.+1 ptr. of T-list
;       byte6:  sema first el. ptr of wait list
;       byte7:  sema last el. ptr of wait list
;
;       Index to the array is the mailbox number or the internal semaphore number

?RTX_MBX_CONTROL_BASE:          DS      8*8

;
;       Array of semaphore tokens
;       -------------------------
;
;       Index is internal semaphore number
;       =0:     no token stored
;       =1:     token is stored
;       else:   not allowed value
;       (initialised to 0)
;
?RTX_SEM_TOKENS:                DS      8

;
;       INT_TID Table
;       -------------
;
;       Interrupt owner list.
;
?RTX_INT_TID_TABLE_BASE:
?RTX_INT0_TID:       DS       1              ; Interrupt owner list (#=0..15)
?RTX_INT1_TID:       DS       1              ;
?RTX_INT2_TID:       DS       1              ;
?RTX_INT3_TID:       DS       1              ;
?RTX_INT4_TID:       DS       1              ;
?RTX_INT5_TID:       DS       1              ;
?RTX_INT6_TID:       DS       1              ;
?RTX_INT7_TID:       DS       1              ;
?RTX_INT8_TID:       DS       1              ;
?RTX_INT9_TID:       DS       1              ;
?RTX_INT10_TID:      DS       1              ;
?RTX_INT11_TID:      DS       1              ;
?RTX_INT12_TID:      DS       1              ;
?RTX_INT13_TID:      DS       1              ;
?RTX_INT14_TID:      DS       1              ;
?RTX_INT15_TID:      DS       1              ;

?RTX_INT16_TID:      DS       1              ; Interrupt owner list (#=16..31)
?RTX_INT17_TID:      DS       1              ;
?RTX_INT18_TID:      DS       1              ;
?RTX_INT19_TID:      DS       1              ;
?RTX_INT20_TID:      DS       1              ;
?RTX_INT21_TID:      DS       1              ;
?RTX_INT22_TID:      DS       1              ;
?RTX_INT23_TID:      DS       1              ;
?RTX_INT24_TID:      DS       1              ;
?RTX_INT25_TID:      DS       1              ;
?RTX_INT26_TID:      DS       1              ;
?RTX_INT27_TID:      DS       1              ;
?RTX_INT28_TID:      DS       1              ;
?RTX_INT29_TID:      DS       1              ;
?RTX_INT30_TID:      DS       1              ;
?RTX_INT31_TID:      DS       1              ;

?RTX_SYS_PAGE_END:   DS       0


;---------------AUXILIARY_PAGE---------------------------------------

?RTX?RTX_AUX_PAGE    SEGMENT XDATA INPAGE
                     RSEG    ?RTX?RTX_AUX_PAGE

?RTX_AUX_PAGE:           DS    0

?RTX_KNTXT_PTR_TABLE:    DS    2*(TASK_COUNT-3); PTR. to Non-Driver Kontext
?RTX_TID_TABLE:          DS    TASK_COUNT      ; Active tasks TID table

;
;       Delay/interval list
;       -------------------
;
;       Restriction: - Size of each sublist must be TASK_COUNT
;                    - Order of sublists must not be changed
;

?RTX_DELAY_LIST_CLK:     DS    TASK_COUNT      ; List for delayed tasks (used
?RTX_DELAY_LIST_TID:     DS    TASK_COUNT      ; by system clock functions)
?RTX_INTERVAL_LIST:      DS    TASK_COUNT      ; Last wake-up time list 

?RTX_SYS_TICK:           DS    2               ; System clock reload value
?RTX_ISR_LIFO:           DS    ISR_LIFO_SIZE   ; LIFO for ISR-Functions
?RTX_POOL_CONTR:         DS    6*(NBR_OF_POOLS); Control-Field for the
                                               ; memory-pools
?RTX_INTERNAL_NUM_TABLE: DS    TASK_COUNT      ; internal to external task-num
?RTX_DEBUG_TID:          DS    1               ; (used by DBG2 version of
                                               ; RTX-51 only)
?RTX_AUX_PAGE_END:       DS    0


;---------------MAILBOX_PAGE-----------------------------------------

; --> see RTXCONF.A51 !

;---------------SEMAPHORE_PAGE---------------------------------------

; --> see RTXCONF.A51 !

;--------------------------------------------------------------------
;
;   END OF MODULE
;
	END
